When Heat Becomes the Binding Constraint: What Packaging Thermal Limits Mean for OEM and EMS Sourcing Through 2027

The memory cycle has dominated AI infrastructure sourcing since 2025, and with good reason. Allocation mechanics for HBM, contract repricing across DDR5 and enterprise NAND, and the widening gap between contract and spot quotations gave procurement organisations a clear, if uncomfortable, model of where programme risk originated. That model has been sufficient for roughly two planning cycles. The public discussion this week suggests it is no longer sufficient, because the constraint that determines whether a rack ships has moved out of the memory column entirely.

Seoul National University Professor Kim Sung-dong framed the change in ordering terms rather than in degree, noting that the industry now prioritises thermal management over further performance gains. That is a materially different statement from an observation that cooling has become harder. It positions heat as the precondition that governs whether compute and memory content can be deployed at all, which places thermal hardware upstream of the semiconductor content in the programme dependency graph. KAIST Professor Kim Joung-ho located the mechanism in 3D stacking, where increasing stack height concentrates heat flux while lengthening the dissipation path, and described using an HBM Design AI Agent in his lab to search heat-dissipation structures through AI-driven design automation and digital twins rather than manual iteration.

The quantitative picture supports the reordering. Individual AI processors from NVIDIA, AMD and Google have each crossed 1kW TDP, and rack-scale systems now draw hundreds of kilowatts, an envelope that approaches the total consumption of a small legacy data centre in a single cabinet. Liquid cooling penetration moves from roughly 33% in 2025 to 53% in 2026, approaching 60% in 2027. The 2026 figure is the operationally important one, because a penetration rate above half means liquid cooling has become the default rack architecture rather than a premium configuration, and any quotation template or capacity model still assuming air cooling as the base case will produce systematically wrong answers for the second half of this year.

For OEM and EMS organisations, the sourcing consequence is a widening of the critical path rather than a substitution within it. Cold plates are dimensionally bound to package geometry and refresh on the accelerator cadence, which limits cross-generation reuse and compresses the qualification window each time silicon changes. Pump assemblies, including redundant configurations, carry reliability class requirements that keep the qualified supplier list short. Quick-disconnects tie leak risk directly to rack downtime, which lengthens qualification cycles well beyond what their unit cost would suggest. High-voltage DC power components enter as a genuinely new category, because rack power in the hundreds of kilowatts is changing the distribution architecture itself and pulling busbar and protection hardware into the critical BOM.

What these categories share is a profile that conventional semiconductor sourcing structures handle poorly. Unit costs are low relative to accelerator and memory content, which historically kept them outside executive-level programme reviews. Supplier bases are narrow and often sit outside franchised semiconductor distribution, so the escalation paths and allocation relationships built over the past two years do not apply. And absence of any single item prevents shipment of the complete system, which means their risk contribution is not proportional to their spend. Programme governance that reviews memory allocation weekly while treating thermal hardware as a commodity line item is now misallocating attention against the actual risk distribution.

Three mitigation paths are under active discussion, and each is credible on its own terms while sharing a timing problem. Co-packaged optics moves optical transceivers into the processor package and substitutes optical signalling for copper interconnect, which reduces thermal load as a direct consequence of the architecture. SK hynix published a CPO roadmap in Nature Electronics on 20 August, developed with international researchers including University of Virginia Professor Kyusang Lee, targeting over 100 Tb/s of bandwidth per node, sub-1 pJ/bit efficiency and chip-to-chip latency below 10ns, with the development path spanning 2D packaging, 2.5D interposers and 3D heterogeneous integration. System-technology co-optimization approaches the same constraint from the design side, pulling thermal limits forward into system architecture rather than optimising components in isolation. New memory tiers, specifically HBF built on stacked NAND and HBS built on stacked SRAM, are expected to appear alongside HBM, and Samsung's zHBM claims 10x density against HBM5, a 3x energy-efficiency gain and thermal-resistance reduction above 50%.

None of these paths alters 2026 or 2027 build schedules. The CPO roadmap explicitly spans three packaging generations, and the new memory tiers sit in a next-generation product sequence. This is where the supply-side constraint compounds the problem rather than relieving it, because advanced packaging capacity is itself governed by equipment lead times now running 12 months for conventional etch and deposition, over 18 months for high-end back-end tools and 24 months for RF power supplies. The engineering solutions to a thermal problem require packaging capacity that arrives on the same delayed curve as everything else.

The same week offered a useful contrast in timelines. Samsung HBM4 yield improved from below 60% at February 2026 mass-production start to approximately 80%, and the company scheduled groundbreaking on a KRW 6 trillion Onyang HBM fab for September, with Pyeongtaek P5 moving to a triple-fab structure at 1.5x revised capacity and 2030 completion. The yield improvement is the component deliverable inside 2026; the fab output falls after 2029 on standard three-year-plus construction-to-production timelines. Supply-side increments and thermal-side constraints are therefore operating on genuinely separate clocks, and conflating them produces build plans that are optimistic on both dimensions simultaneously.

The practical conclusion for sourcing organisations is narrow and specific. AI server programmes entering design freeze in the second half of 2026 warrant thermal and power-delivery hardware carried as first-class BOM entries with independent lead-time tracking and named qualified suppliers, on the same review cadence currently applied to memory allocation. Rack proposals with delivery beyond 2027 are more safely quoted on a liquid-cooling default. And the assumption that compute-component lead time defines the programme critical path, which held reasonably well through 2025, no longer describes where these projects actually fail.