CoWoS-L Becomes the Mainstream Route Beyond Reticle Limits as AI Packages Add Chiplets and HBM

Reticle limits move into system planning

TrendForce's September 18, 2026 analysis places package dimensions at the center of the next AI accelerator cycle. GPU vendors and hyperscale cloud providers continue to combine more compute functions, HBM stacks and high-speed interfaces in one module. CoWoS-S connects compute dies and HBM through a silicon interposer, but larger designs are approaching practical exposure and manufacturing boundaries for a monolithic interposer.

This physical limit propagates into commercial planning. Larger modules require more complex routing, power delivery, thermal control, substrate construction and final test. They also concentrate component value: a late package defect can strand several qualified compute dies and multiple HBM stacks. The economically relevant yield is therefore the yield of the complete module, not the isolated wafer result of any single component.

CoWoS-L expands the integration envelope

TrendForce states that CoWoS-S can integrate two SoCs or chiplets and eight HBM modules and remains appropriate for designs such as Microsoft Maia 200. Architectures that require more compute dies and memory stacks need a larger integration envelope. CoWoS-L uses embedded high-speed silicon bridge dies within the interposer structure, providing dense local connections while supporting a broader package footprint.

NVIDIA and AMD accelerators already use CoWoS-L, as does Meta MTIA 400. AWS and Microsoft are expected to adopt it in 2027. These programs validate the technology direction, but each implementation retains unique die maps, HBM configurations, substrate rules and test flows. Capacity cannot be transferred between programs without qualification and design compatibility.

HBM and packaging capacity form one constraint

HBM expansion increases bandwidth and capacity but also raises current density, cooling requirements and routing complexity. Interposer line density, microbump pitch, substrate layers and power integrity must be solved together. A shortfall in substrate capability or final test can delay output even when compute wafers and HBM stacks are available.

For OEM and EMS programs, the supply unit is a qualified module configuration. Known-good-die controls, assembly slots, thermal materials, package yield and system validation determine shipment readiness. Separate inventories of processors and memory do not represent equivalent finished capacity. Allocation analysis therefore needs package-family and customer-program detail.

EMIB-T offers a different cost structure

The larger interposer required by CoWoS-L adds cost. Persistent pressure on TSMC advanced-packaging capacity also encourages customers to evaluate Intel EMIB. EMIB embeds local silicon bridges in the substrate, reducing dependence on a large full silicon interposer. The architecture can lower interposer area and material cost, although substrate routing density becomes a more prominent performance constraint.

Intel is refining line-and-space and microbump specifications and developing EMIB-T with through-silicon vias. TSVs shorten signal paths and improve module performance. TrendForce expects Google to adopt EMIB-T in 2027, and AWS is testing EMIB. These evaluations create a second route, but switching requires architectural adaptation, package-rule conversion and a new reliability and system qualification cycle.

Demand broadens through 2027

TrendForce expects NVIDIA high-end GPU shipments to increase roughly 30% year over year in 2026. AMD is promoting MI400 and MI450 from the second half of the year. Google TPU v7 is expected to lead cloud ASIC shipment volume and growth, while AWS transitions AI server systems toward Trainium v3. Microsoft and Meta remain more dependent on GPU servers, although custom silicon programs continue.

The mix matters because each product consumes a different package configuration. Large training accelerators may require more HBM and interposer area than an inference ASIC. Announced expansion should be separated by process, package family, qualified customer and ramp yield. Gross assembly starts cannot be treated as finished qualified output.

CoWoS-L retains the maturity advantage

TrendForce expects CoWoS-L to remain the mainstream advanced-packaging solution for AI chips through 2028 because of technology maturity and yield. Its installed production base, supplier learning and existing platform wins lower execution risk. EMIB-T can compete where interposer cost, local bridging or supplier diversification carries greater weight, but its routing and ecosystem performance require program-level evidence.

Coexistence is the likely market structure. GPUs, cloud ASICs and rack-scale systems do not share identical optimization targets. Density, cost, schedule, thermal limits and supplier concentration receive different priorities. Platform adoption will therefore be distributed across several packaging paths rather than converging on one universal structure.

Evidence for procurement decisions

The highest-value checkpoints are qualified CoWoS-L ramp capacity, substrate vendor readiness, HBM stack count, EMIB-T tape-outs, reliability completion and final-test throughput. OEM launch schedules and committed production dates carry more weight than broad capacity forecasts. Package-level yield and validated configuration determine deliverable supply.

Advanced-packaging tightness also remains segmented. CoWoS-L serves large AI accelerators and selected cloud ASICs; it does not share every constraint with analog, MCU, power or mainstream consumer packages. Product-specific evidence prevents an AI packaging bottleneck from being misread as a universal semiconductor assembly shortage.

A synchronized supply chain

The central change is synchronization. Compute dies, HBM, bridges, substrates, thermal materials, assembly and test must reach target yield at the same time. Capacity at one stage cannot compensate for an unqualified or low-yield stage elsewhere. The resulting supply profile is narrower than aggregate fab or packaging statistics suggest.

CoWoS-L and EMIB-T represent different methods for extending that integration envelope. Their commercial significance will be measured by repeatable package yield, platform qualification and committed delivery rather than architectural claims alone. Through 2028, maturity favors CoWoS-L, while customer qualification will determine the addressable share for EMIB-T.